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2M x 32-Bit Dynamic RAM Module
HYM 322030S/GS-50/-60/-70
Advanced Information
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2 097 152 words by 32-bit organization 1 memory bank Fast access and cycle time 50 ns access time 90 ns cycle time (-50 version) 60 ns access time 110 ns cycle time (-60 version) 70 ns access time 130 ns cycle time (-70 version) Fast page mode capability 35 ns cycle time (-50 version) 40 ns cycle time (-60 version) 45 ns cycle time (-70 version) Single + 5 V ( 10 %) supply Low power dissipation max. 2640 mW active (-50 version) max. 2420 mW active (-60 version) max. 2200 mW active (-70 version) CMOS - 22 mW standby TTL -44 mW standby CAS-before-RAS refresh RAS-only-refresh Hidden-refresh 4 decoupling capacitors mounted on substrate All inputs, outputs and clocks fully TTL compatible 72 pin Single in-Line Memory Module (L-SIM-72-9 ) with 20.32 mm (800 mil) height Utilizes four 2M x 8 -DRAMs in 400 mil SOJ packages 2048 refresh cycles / 32 ms with 11/10 addressing Optimized for use in byte-write non-parity applications Tin-Lead contact pads (S-version) Gold contact pads (GS - version)
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Semiconductor Semicunductor Group
1
9.95
HYM 322030S/GS-50/-60/-70 2M x 32-Bit
The HYM 322030S/GS-50/-60/-70 is a 8 MByte DRAM module organized as 2 097 152 words by 32-bit in a 72-pin single-in-line package comprising four HYB 5117800BSJ 2M x 8 DRAMs in 400 mil wide SOJ-packages mounted together with four 0.2 F ceramic decoupling capacitors on a PC board. Each HYB 5117800BSJ is described in the data sheet and is fully electrical tested and processed according to SIEMENS standard quality procedure prior to module assembly. After assembly onto the board, a further set of electrical tests is performed. The speed of the module can be detected by the use of four presence detect pins. The common I/O feature on the HYM 322030S/GS-60/-70 dictates the use of early write cycles. Ordering Information Type HYM 322030S-50 HYM 322030S-60 HYM 322030S-70 HYM 322030GS-50 HYM 322030GS-60 HYM 322030GS-70 Ordering Code on request Q67100-Q976 Q67100-Q977 on request Q67100-Q2018 Q67100-Q2019 Package L-SIM-72-9 L-SIM-72-9 L-SIM-72-9 L-SIM-72-9 L-SIM-72-9 L-SIM-72-9 Description DRAM Module (access time 50 ns) DRAM Module (access time 60 ns) DRAM Module (access time 70 ns) DRAM Module (access time 50 ns) DRAM Module (access time 60 ns) DRAM Module (access time 70 ns)
Semiconductor Group
2
HYM 322030S/GS-50/-60/-70 2M x 32-Bit
Pin Configuration
Pin Names
VSS DQ16 DQ17 DQ18 DQ19 N.C. A1 A3 A5 A10 DQ20 DQ21 DQ22 DQ23 N.C. A8 N.C. N.C. N.C. VSS CAS2 CAS1 N.C. WE DQ8 DQ9 DQ10 DQ11 DQ12 VCC DQ13 DQ14 DQ15 PD0 PD2 N.C. 1 DQ0 2 3 DQ1 4 5 DQ2 6 7 DQ3 8 9 VCC 10 11 A0 12 13 A2 14 15 A4 16 17 A6 18 19 DQ4 20 21 DQ5 22 23 DQ6 24 25 DQ7 26 27 A7 28 29 VCC 30 31 A9 32 33 RAS2 34 35 N.C. 36 37 N.C. 38 39 CAS0 40 41 CAS3 42 43 RAS0 44 45 N.C. 46 47 N.C. 48 49 DQ24 50 51 DQ25 52 53 DQ26 54 55 DQ27 56 57 DQ28 58 59 DQ29 60 61 DQ30 62 63 DQ31 64 65 N.C. 66 67 PD1 68 69 PD3 70 71 VSS 72
A0R-A10R A0C-A9C DQ0-DQ31 CAS0 - CAS3 RAS0, RAS2 WE
Row Address Inputs Column Address Inputs Data Input/Output Column Address Strobe Row Address Strobe Read/Write Input Power (+ 5 V) Ground Presence Detect Pin No Connection
VCC VSS
PD N.C.
Presence Detect Pins -50 PD0 PD1 PD2 PD3 N.C. N.C. -60 N.C. N.C. N.C. N.C. -70 N.C. N.C.
VSS VSS
VSS
N.C.
Semiconductor Group
3
HYM 322030S/GS-50/-60/-70 2M x 32-Bit
RAS0 CAS0 CAS DQ0-DQ7 I/O1-I/O8 OE D1 RAS
CAS1 CAS DQ8-DQ15 I/O1-I/O8 OE D2 RAS
RAS2 CAS2 CAS DQ16-DQ23 I/O1-I/O8 OE D3 RAS
CAS3 CAS DQ24-DQ31 I/O1-I/O8 OE D4 RAS
A0R - A10R, A0C - A9C WE VCC C1 - C 4 VSS
D1 - D4 D1 - D4
Block Diagram
Semiconductor Group
4
HYM 322030S/GS-50/-60/-70 2M x 32-Bit
Absolute Maximum Ratings Operation temperature range ......................................................................................... 0 to + 70 C Storage temperature range......................................................................................... - 55 to 125 C Input/output voltage ............................................................................-0.5V to min (Vcc+0.5, 7.0) V Power supply voltage...................................................................................................... - 1 to + 7 V Power dissipation..................................................................................................................... 4.2 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics TA = 0 to 70 C, VCC = 5 V 10 % Parameter Symbol Limit Values min. Input high voltage Input low voltage Output high voltage (IOUT = - 5 mA) Output low voltage (IOUT = 4.2 mA) Input leakage current (0 V < VIN < 6.5 V, all other pins = 0 V) Output leakage current (DO is disabled, 0 V < VOUT < 5.5 V) Average VCC supply current (RAS, CAS, address cycling, tRC = tRC min) -50 version -60 version -70 version Standby VCC supply current (RAS = CAS = VIH) Average VCC supply current during RAS only refresh cycles (RAS cycling, CAS = VIH, tRC = tRC min) -50 version -60 version -70 version max. Vcc+0.5 0.8 - 0.4 10 10 V V V V A A Unit Test Condition
1) 1) 1) 1) 1)
VIH VIL VOH VOL II(L) IO(L) ICC1
2.4 - 0.5 2.4 - - 10 - 10
1)
- - -
480 440 400 8
mA mA mA mA
2),3),4)
ICC2 ICC3
-
- - -
480 440 400
mA mA mA
2), 4)
Semiconductor Group
5
HYM 322030S/GS-50/-60/-70 2M x 32-Bit
DC Characteristics1) (cont'd) Parameter Average VCC supply current during fast page mode (RAS = VIL, CAS, address cycling, tPC = tPC min) -50 version -60 version -70 version Standby VCC supply current (RAS = CAS = VCC - 0.2 V) Average VCC supply current during CAS-before-RAS refresh mode (RAS, CAS cycling, tRC = tRC min) -50 version -60 version -70 version Symbol Limit Values min. max. Unit Test Condition
ICC4
- - -
160 140 120 4
mA mA mA mA
2), 3), 4)
ICC5 ICC6
-
- - -
480 440 400
mA mA mA
2), 4)
Capacitance
TA = 0 to 70 C, VCC = 5 V 10 %, f = 1 MHz
Parameter Symbol Limit Values min. Input capacitance (A0 to A11) Input capacitance (RAS0, RAS2) Input capacitance (CAS0 - CAS3) Input capacitance (WE) I/O capacitance (DQ0-DQ31) max. 40 45 45 45 25 pF pF pF pF pF Unit
CI1 CI2 CI3 CI4 CIO
- - - - -
Semiconductor Group
6
HYM 322030S/GS-50/-60/-70 2M x 32-Bit
AC Characteristics 5)6) TA = 0 to 70 C,VCC = 5 V 10 %, tT = 5 ns Parameter
Symbol
16F
Limit Values -50 min. -60 -70 max. - - 10k 10k - - - - 50 35 - - - 50 32
Unit Note
max. min. - - 10k 10k - - - - 37 25 110 40 60 15 0 10 0 15 20 15 15 60 - 50 32 5 3 -
max. min. - - 10k 10k - - - - 45 30 - - - 50 32 130 50 70 20 0 10 0 15 20 15 20 70 5 3 -
common parameters
Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Refresh period tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tT tREF 90 30 50 13 0 8 0 10 18 13 13 50 5 3 - ns ns ns ns ns ns ns ns ns ns ns ns ns ms 7
Read Cycle
Access time from RAS Access time from CAS tRAC tCAC - - - 25 0 0 0 0 0 50 13 25 - - - - - 13 - - - 30 0 0 0 0 0 60 15 30 - - - - - 15 - - - 35 0 0 0 0 0 70 20 35 - - - - - 20 ns ns ns ns ns ns ns ns ns 11 11 8 12 8, 9 8, 9 8,10
Access time from column address tAA Column address to RAS lead time tRAL Read command setup time Read command hold time Read command hold time referenced to RAS CAS to output in low-Z Output buffer turn-off delay tRCS tRCH tRRH tCLZ tOFF
Semiconductor Group
7
HYM 322030S/GS-50/-60/-70 2M x 32-Bit
AC Characteristics (cont'd) 5)6) TA = 0 to 70 C,VCC = 5 V 10 %, tT = 5 ns Parameter
Symbol
16F
Limit Values -50 min. -60 -70 max. - - - - - - -
Unit Note
max. min. - - - - - - - 10 10 0 15 15 0 10
max. min. - - - - - - - 10 10 0 20 20 0 15
Early Write Cycle
Write command hold time Write command pulse width Write command setup time tWCH tWP tWCS 8 8 0 13 13 0 10 ns ns ns ns ns ns ns 16 16 15
Write command to RAS lead time tRWL Write command to CAS lead time tCWL Data setup time Data hold time tDS tDH
Fast Page Mode Cycle
Fast page mode cycle time CAS precharge time Access time from CAS precharge RAS pulse width CAS precharge to RAS Delay tPC tCP tCPA tRAS tRHPC 35 10 - 50 30 - - 30 - 40 10 - 35 - - 35 - 45 10 - 40 - - 40 - ns ns ns ns 7
200k 60
200k 70
200k ns
CAS-before-RAS Refresh Cycle
CAS setup time CAS hold time RAS to CAS precharge time Write to RAS precharge time tCSR tCHR tRPC tWRP 10 10 5 10 - - - - 10 10 5 10 - - - - 10 10 5 10 - - - - ns ns ns ns
Semiconductor Group
8
HYM 322030S/GS-50/-60/-70 2M x 32-Bit
Notes:
1) All voltages are referenced to VSS. 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. 4) Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less during a fast page mode cycle (tPC). 5) An initial pause of 200 s is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 5 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8) Measured with a load equivalent to 2 TTL loads and 100 pF. 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10)Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11)Either tRCH or tRRH must be satisfied for a read cycle. 12)tOFF (max.) define the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels . 13)tWCS is not a restrictive operating parameter. This is included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin will remain open-circuit (high impedance) through the entire cycle. 14)These parameters are referenced to the CAS leading edge.
Semiconductor Group
9
HYM 322030S/GS-50/-60/-70 2M x 32-Bit
Package Outline
Dimensions in mm
GLS05789
Module Package L-SIM-72-9 (Single in-Line Memory Module)
Semiconductor Group
10

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